Method for fabricating light-emitting diode using nanosize nitride semiconductor multiple quantum wells

ABSTRACT

Disclosed is a III-nitride compound semiconductor nanophase opto-electronic cell, comprising a silicon substrate ( 100 ), and an amorphous silicon nitride layer (base) ( 200 ) formed on the substrate and including III-nitride compound semiconductor nano grains ( 230 ) spontaneously formed therein. The nitride semiconductor nanophase opto-electronic cell and the fabrication method thereof according to the present invention are free from the problems of the conventional III-nitride compound semiconductor thin film growth on silicon substrates. Accordingly, a high-quality III-nitride compound semiconductor nanophase opto-electronic cell having no crystalline defect can be provided. Furthermore, the opto-electronic cell according to the present invention does not require a p-type GaN thin film so that there is no possibility of causing crack that is a problem in the conventional method of fabricating a III-nitride compound semiconductor opto-electronic cell using III-nitride thin films grown on silicon substrates. In addition, the number of processes of fabricating the cell is remarkably reduced to result in an economical and productive opto-electronic cell fabrication process.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a III-nitride compound semiconductor (Al_(x)In_(y)Ga_(1-x-y)N, 0≦x,y≦1) nanophase opto-electronic cell and a fabrication method thereof, and more particularly, to a III-nitride compound semiconductor nanophase opto-electronic cell having an amorphous silicon nitride (SiN_(x)) layer (base) 200 including III-nitride compound semiconductor nanocrystals 230 spontaneously formed and a fabrication method thereof.

[0003] 2. Background of the Related Art

[0004] An optical device or an electronic device based on III-nitride compound semiconductors (Al_(x)In_(y)Ga_(1-x-y)N, 0≦x,y≦1) is fabricated in such a manner that a high-quality gallium nitride (GaN) thin film is basically grown on a sapphire substrate. The problem in this fabrication method is that sapphire that is expensive, hard and insulated is used as the substrate. Accordingly, the development of a substrate capable of replacing sapphire is required. The most typical substitute substrate is a silicon substrate. Studies on the silicon substrate are being widely carried out because the silicon substrate is cheap and conductive and it has an advantage in that a well-advanced electronic device based on silicon and an optical device based on gallium nitride (GaN) can be integrated with each other on the silicon substrate.

[0005]FIG. 1 is a schematic cross-sectional view of a conventional nitride semiconductor opto-electronic cell.

[0006] As shown in FIG. 1, the conventional nitride semiconductor opto-electronic cell is fabricated in such a manner that an n-type GaN 11 is deposited on a silicon substrate 10, a multiple quantum well composed of an InGaN 13 and a GaN 14 is formed on the n-type GaN 11 into an active layer 12, a p-type GaN 15 is formed thereon, and negative and positive metal electrodes 16 and 17 are formed on the n-type GaN and the p-type GaN, respectively. That is, the cell includes an n-type GaN layer, an active layer and a p-type GaN thin film as basic constituent elements.

[0007] However, the growth of the GaN thin film on the silicon substrate 10 has the following problems.

[0008] Firstly, silicon crystal and GaN crystal have a relatively large lattice mismatch of about 17% therebetween and a big difference in thermal expansion coefficient of 37% therebetween. These seriously deteriorate the quality of the GaN thin film formed on the silicon substrate.

[0009] Secondly, the growth of the GaN thin film having high quality on the silicon substrate is needed to integrate a silicon based electronic device and a GaN based optical device. However, the silicon substrate has a cubic crystalline structure and the GaN grown by a general technique has a hexagonal crystalline structure so that it is basically difficult to grow the high-quality GaN thin film on the silicon substrate due to a difference in crystalline structure.

[0010] Thirdly, an amorphous silicon nitride layer is spontaneously formed on the surface of the silicon substrate due to an undesired chemical reaction when the GaN thin film is grown on the silicon substrate, which makes it difficult to grow a high-quality GaN thin film.

[0011] Fourthly, in order to form the p-type GaN thin film having a high hole concentration, a technique for growing the high-quality GaN thin film is needed and the grown thin film should be thermally treated at a high temperature. This post-thermal treatment at a high-temperature for activating such a p-type dopant causes serious cracks on the thin film due to a large difference in thermal expansion coefficient between the GaN thin film and the silicon substrate.

SUMMARY OF THE INVENTION

[0012] An object of the present invention is to provide a high-quality nitride semiconductor nanophase opto-electronic cell having no crystalline defect and a fabrication method thereof.

[0013] Another object of the present invention is to provide a nitride semiconductor nanophase opto-electronic cell requiring no p-type GaN thin film and a fabrication method thereof.

[0014] To accomplish the objects of the present invention, there is provided a nitride semiconductor nanophase opto-electronic cell comprising: a silicon substrate 100; and an amorphous silicon nitride layer (base) 200 formed on the substrate 100 and including III-nitride compound semiconductor nano grains 230 spontaneously formed therein.

[0015] To accomplish the objects of the present invention, there is also provided a method of fabricating an opto-electronic cell using a III-nitride compound semiconductor, comprising the steps of: growing an amorphous silicon nitride (SiN_(x)) layer on a silicon substrate; growing III-nitride compound semiconductor nanostructures on the amorphous silicon nitride layer; and growing an amorphous silicon nitride cover layer on the amorphous silicon nitride layer and the nitride semiconductor nanostructures grown on the amorphous silicon nitride layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments of the invention in conjunction with the accompanying drawings, in which:

[0017]FIG. 1 is a schematic cross-sectional view showing the structure of a conventional nitride semiconductor opto-electronic cell;

[0018]FIG. 2 is a schematic cross-sectional view showing the structure of a nitride semiconductor nanophase opto-electronic cell in which an amorphous silicon nitride layer (base) has nitride semiconductor nano grains formed therein according to the present invention;

[0019]FIG. 3 is a schematic cross-sectional view showing the structure of a nitride semiconductor nanophase opto-electronic cell in which multiple quantum wells are formed on nano grains of Al_(x)In_(y)Ga_(1-x-y)N (0≦x,y≦1) according to the present invention;

[0020]FIG. 4 is a SEM picture of GaN nanocrystals grown on a thermally nitrided p-type silicon substrate according to the present invention;

[0021]FIG. 5 is a graph showing the room-temperature optical characteristic spectrum of InGaN nanocrystals imbedded in the amorphous silicon nitride according to the present invention;

[0022]FIG. 6 is a graph showing the room-temperature optical characteristic spectrum of a InGaN/GaN multiple quantum wells imbedded in the amorphous silicon nitride according to the present invention;

[0023]FIG. 7 is a graph showing the current-voltage characteristic of a resonant tunneling light-emitting diode composed of InGaN/GaN multiple quantum well nanocrystals;

[0024]FIG. 8 is a schematic cross-sectional view showing the structure of the diode of FIG. 7;

[0025]FIG. 9 is a schematic cross-sectional view showing the structure of one of the multiple quantum wells of FIG. 8; and

[0026]FIG. 10 is a schematic cross-sectional view showing the structure of a nitride semiconductor nanophase opto-electronic cell in which the amorphous silicon nitride cover layers having multiple quantum wells are disposed on the amorphous silicon nitride cover layer in the form of a multi-layered structure according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0027] A III-nitride compound semiconductor nanophase opto-electronic cell and a fabrication method thereof according to the present invention will be described in detail hereinafter.

[0028] Distinguished from the conventional method of growing the GaN thin film on the silicon substrate 100, the present invention is based on a new method of embedding GaN nanophase material in an amorphous silicon nitride, that is, spontaneously forming nitride semiconductor nanophase having a nanometer size in an amorphous silicon nitride layer (base) 200 grown on a silicon substrate 100 [J. Crystal Growth 248, 494 (2003)].

[0029] The nitride semiconductor nanophase opto-electronic cell according to the present invention includes a silicon substrate 100 and an amorphous silicon nitride layer (base) 200 formed on the substrate 100 and including nitride semiconductor nano grains 230 spontaneously formed therein, the nitride semiconductor nano grains 230 serving as an active layer.

[0030]FIG. 2 is a schematic cross-sectional view showing the structure of a nitride semiconductor nanophase opto-electronic cell in which an amorphous silicon nitride layer (base) 200 has III-nitride compound semiconductor nano grains 230 formed therein according to the present invention.

[0031] As shown in FIG. 2, the amorphous silicon nitride layer (base) 200 of the nitride semiconductor nanophase opto-electronic cell of the invention is preferably composed of an amorphous silicon nitride layer 210, nitride semiconductor nano grains 230 spontaneously formed on the amorphous silicon nitride layer 210, and an amorphous silicon nitride cover layer 220 formed on the amorphous silicon nitride layer 210 and the spontaneously formed the nitride semiconductor nano grains 230.

[0032] The III-nitride compound semiconductor nano grains 230 are nano particles of Al_(x)In_(y)Ga_(1-x-y)N (0≦x, y≦1) or nano particles of Al_(x)In_(y)Ga_(1-x-y)N/Al_(i)In_(j)Ga_(1-i-j)N (0≦x, y, i, j≦1) forming a multiple quantum well structure. The multiple quantum well structure can be grown on nano grains of Al_(x)In_(y)Ga_(i-x-y)N (0≦x, y≦1).

[0033]FIG. 3 is a schematic cross-sectional view showing the structure of a nitride semiconductor nanophase opto-electronic cell in which multiple quantum wells are formed on nano grains of Al_(x)In_(y)Ga_(1-x-y)N (0≦x, y≦1) according to the present invention.

[0034] Referring to FIG. 3, an amorphous silicon nitride layer 210 is formed on a silicon substrate 100, and nano grains 231 of Al_(x)In_(y)Ga_(1-x-y)N (0≦x, y≦1) are spontaneously formed on the amorphous silicon nitride layer 210. In addition, multiple quantum wells (nanophase) 300 are grown on the nano grains and the cover layer 220 is formed on the multiple quantum wells (nanophase) 300 and the amorphous silicon nitride layer 210. Preferably, the diameter of the nano grain of Al_(x)In_(y)Ga_(1-x-y)N (0≦x, y≦1) is 1 to 500 nm. In the case where the diameter of the nano grain is larger than 500 nm, it is difficult to completely cover the nano grains with the cover layer and the density of the nano grains is considerably decreased. Furthermore, when the diameter of the nano grain is smaller than 1 nm, the nano grains are not thermodynamically stabilized.

[0035] In case of the multiple quantum well structure, it is preferable that the diameter of the nano grain of Al_(x)In_(y)Ga_(1-x-y)N/Al_(i)In_(j)Ga_(1-i-j)N (0≦x, y, i, j≦1) is 3 to 500 nm such that one to twenty pairs of layers, each layer having the thickness of 1 to 20 nm, are repeatedly laminated.

[0036] The multiple quantum well structure can exhibit satisfactory quantum confinement effect when each of the layers constructing the multiple quantum wells has the thickness of 1 to 20 nm or so. Furthermore, when a quantum well having a small energy gap and a quantum barrier having a large energy gap are laminated in multiple layers, carriers are effectively confined in the quantum wells so that optical and electrical performances of the cell can be remarkably improved. When the number of the layers exceeds twenty, a crystal defect is caused to deteriorate the performance of the cell.

[0037] More preferably, the nitride semiconductor nanophase opto-electronic cell according to the present invention is fabricated in such a manner that an electron injection layer (not shown) is formed on the amorphous silicon nitride layer (base) 200.

[0038] As a preferred example, the amorphous silicon nitride layer (base) 200 including the spontaneously formed nitride semiconductor nano grains of Al_(x)In_(y)Ga_(1-x-y)N (0≦x, y≦1) the diameter of which is 1 to 500 nm or multiple quantum well nano grains composed of one to twenty pairs of Al_(x)In_(y)Ga_(1-x-y)N/Al_(i)In_(j)Ga_(1-i-j)N (0≦x, y, i, j≦1) that are nanometers in size is formed as an active layer on a p-type silicon substrate 100, and n-type Al_(x)In_(y)Ga_(1-x-y)N (0≦x, y≦1) that is 1 to 500 nm in thickness is formed as an electron injection layer (not shown) on the amorphous silicon nitride layer.

[0039] The amorphous silicon nitride cover layer 220 has low carrier mobility so that electrons injected through the negative metal electrode cannot be laterally diffused from the cover layer. On the other hand, the electron injection layer (not shown) has high carrier mobility so that injected electrons can be laterally and widely diffused. Thus, the carriers can be uniformly diffused and enter the nano grains that is the active layer, thereby improving the performance of the cell.

[0040] Moreover, although it is difficult to inject carriers from the negative metal electrode into the amorphous silicon nitride having a large energy gap, the electron injection layer (not shown) has an energy gap smaller than that of the amorphous silicon nitride so that resistance to the injection of carriers from the metal electrode can be reduced, thereby improving the performance of the device.

[0041] A method of fabricating the nitride semiconductor nanophase opto-electronic cell according to the present invention includes a step (S1) growing an amorphous silicon nitride layer 210 on a silicon substrate 100, a step (S2) of growing nitride semiconductor nano grains 230 on the amorphous silicon nitride layer 210, and a step (S3) of growing an amorphous silicon nitride cover layer 220 on the amorphous silicon nitride layer 210 and the nitride semiconductor nano grains 230 grown on the amorphous silicon nitride layer.

[0042] Preferably, a p-type, p⁺-type, n-type or n⁻-type silicon substrate is used as the substrate 100, and trimethylgallium, trimethylindium, trimethylaluminum and NH₃ are respectively used as sources of gallium, indium, aluminum and nitrogen, used for spontaneously forming the nitride semiconductor nano grains 230.

[0043]FIG. 4 is a SEM picture of GaN nano crystals grown at 900° C. on a thermally nitrided p-type silicon substrate according to the present invention.

[0044] To carry out the step S1, the silicon substrate 100 is nitrided using ammonia. Nitridation of the silicon substrate 100 using ammonia forms an amorphous silicon nitride thin film on the surface of the silicon substrate.

[0045] Preferably, the amorphous silicon nitride layer 210 is formed to have a thickness of 1 to 50 nm at a temperature of 25 to 1100° C. in the step S1.

[0046] When the temperature is higher than 1100° C., thermal decomposition rate of the silicon substrate becomes high. When the temperature is lower than 25° C., mobility of atoms is so low that chemical reaction cannot occur. Probability of resonant tunneling of carriers becomes significantly low when the amorphous silicon nitride layer is thicker than 50 nm, and carriers cannot be effectively confined in terms of quantum mechanics when it is thinner than 1 nm.

[0047] In the step S2, the amorphous silicon nitride layer 210 formed in the step S1 thermodynamically promotes the formation of the nitride semiconductor nano grains thereon. The nitride semiconductor nano grains having the size of nanometer is spontaneously formed in the amorphous silicon nitride layer 210 using chemical vapor deposition (CVD), molecular beam epitaxy (MBE), sputtering system and the like. Here, hydrogen is used as a carrier gas.

[0048] The size and density of the nitride semiconductor nano grains are controlled by the delicate adjustment of growth parameters including growth temperature, growth time, growth gas flow and the like.

[0049] The nitride semiconductor nano grains are formed in such a manner that nano grains of Al_(x)In_(y)Ga_(1-x-y)N (0≦x, y≦1) are grown on the amorphous silicon nitride layer 210 (S2-1), or the multiple quantum wells 300 of Al_(x)In_(y)Ga_(1-x-y)N/Al_(i)In_(j)Ga_(1-i-j)N (0≦x, y, i, j≦1) are formed on the amorphous silicon nitride layer (S2-2), or the nano grains of Al_(x)In_(y)Ga_(1-x-y)N (0≦x, y≦1) is grown and then the multiple quantum well layers 300 of Al_(x)In_(y)Ga_(1-x-y)N/Al_(i)In_(j)Ga_(1-i-j)N (0≦x, y, i, j≦1) are formed on the nano grains (S2-3).

[0050] Preferably, the nano grains of Al_(x)In_(y)Ga_(1-x-y)N (0≦x, y≦1) are grown to have the diameter of 1 to 500 nm at a temperature of 25 to 1100° C. When the temperature is higher than 1100° C., thermal decomposition rate of Al_(x)In_(y)Ga_(1-x-y)N becomes high. When the temperature is lower than 25° C., on the other hand, mobility of atoms is so low that chemical reaction cannot occur.

[0051] The multiple quantum well layers 300 of Al_(x)In_(y)Ga_(1-x-y)N/Al_(i)In_(j)Ga_(1-i-j)N (0≦x, y, i, j≦1) are formed in such a manner that one to twenty pairs of layers are repeatedly deposited at a temperature of 500 to 1100° C. When the temperature is higher than 1100° C., nano grains are difficult to form because thermal decomposition rate of Al_(x)In_(y)Ga_(1-x-y)N becomes high. When the temperature is lower than 500° C., ammonia decomposition efficiency is low and thermal energy required for chemical reaction is insufficient, thereby failing in obtaining a high-quality multiple quantum well structure of Al_(x)In_(y)Ga_(1-x-y)N/Al_(i)In_(j)Ga_(1-i-j)N (0≦x, y, i, j≦1).

[0052] In the step S3, the amorphous silicon nitride cover layer 220 is grown on the amorphous silicon nitride layer 210 and the nitride semiconductor nano grains 230 grown on the amorphous silicon nitride layer 210.

[0053] The GaN nanophase active layer embedded in the amorphous silicon nitride layer 210 can be obtained in such a manner that GaN nano grains are formed on the amorphous silicon nitride, as described above, and then covered with a thin amorphous silicon nitride layer. The amorphous silicon nitride cover layer 220 is grown using a chemical vapor deposition system. Preferably, the amorphous silicon nitride cover layer 220 is 1 to 50 nm in thickness.

[0054] Furthermore, the GaN nano grains embedded in the amorphous silicon nitride layer (base) 200 may be formed in such a manner that an amorphous Ga—Si—N compound layer composed of gallium atoms, silicon atoms and nitrogen atoms is thermally annealed.

[0055] Another method for spontaneously forming the GaN nano grains in the amorphous silicon nitride layer (base) 200 is that a small amount of gallium source gas is added to amorphous silicon nitride being grown by using a silicon source gas and a nitrogen source gas. The GaN nano grains that are spontaneously formed on the growing amorphous silicon nitride layer (base) 200 under the properly controlled growth conditions can be embedded into the continuously growing amorphous silicon nitride layer (base) 200.

[0056] As a preferred example, the GaN nano grains are grown on the nitrided p-type silicon substrate 100, and then InGaN nano grains are grown to have the thickness of approximately 4 nm at a growth temperature reduced to 700 to 800° C. on the substrate 100. The amorphous silicon nitride cover layer 220 having the thickness of about 20 nm is formed on the InGaN nano grains through a chemical vapor deposition method. The amorphous silicon nitride layer (base) including GaN or InGaN nano grains have a large band gap of approximately 5 eV so that it can exhibit an quantum confinement effect for carriers injected into the nano grains.

[0057] The amorphous silicon nitride is more advantageous than silicon oxide as a base material of GaN or InGaN nano grains because oxygen atoms act as a fatal impurity harmful to the material characteristics of the GaN nano grains.

[0058]FIG. 5 is a graph showing the room-temperature optical characteristic spectrum of the InGaN nano grains embedded in the amorphous silicon nitride layer (base) 200 according to the present invention and FIG. 6 is a graph showing the room-temperature optical characteristic spectrum of multiple quantum well structure according to the present invention, in which the multiple quantum well structure is formed in such a manner that GaN nano grains are formed on the nitrided p-type silicon and then a GaN layer with the size of nanometer and a InGaN layer with the size of nanometer are alternately deposited on the GaN nano grains into three layers at a growth temperature reduced to 760° C.

[0059] The multiple quantum well structure is composed of GaN having a large band gap and InGaN having a small band gap, which are alternately deposited, so as to increase the probability of capturing carriers in the InGaN layer by the quantum confinement effect, thereby improving the characteristics of the opto-electronic cell. When the crystal grains, obtained by alternately laminating the InGaN layer and GaN layer with the size of nanometer on the GaN nanophase with the size of nanometer, is embedded in the amorphous silicon nitride layer (base) 200, they can serve as an essential active layer of the opto-electronic cell.

[0060] More preferably, the method of fabricating the nitride semiconductor nanophase opto-electronic cell further includes a step S4 of repeatedly performing a process of growing nano grains of Al_(x)In_(y)Ga_(1-x-y)N (0≦x, y≦1) or multiple quantum well layers (nano grains) 300 on the amorphous silicon nitride cover layer 220 and then forming the amorphous silicon cover layer 220 on the grown nano grains once or twenty times.

[0061]FIG. 10 is a schematic cross-sectional view showing the structure of a nitride semiconductor nanophase opto-electronic cell in which the amorphous silicon nitride cover layers having multiple quantum wells are disposed on the amorphous silicon nitride cover layer in the form of a multi-layered structure according to the present invention.

[0062] As shown in FIG. 10, the structure attained by repeatedly laminating the amorphous silicon nitride layer including the nitride semiconductor nano grains is constructed in such a manner that the amorphous silicon nitride layer 210 is formed on the silicon substrate 100 and the cover layer 220 covering the nitride semiconductor multiple quantum wells (nanophase) 300 is repeatedly deposited on the amorphous silicon nitride layer 210.

[0063] Although injected electrons and holes are confined in the nanophase active layer existing in a single layer to be recombined with each other to emit light, a part of the carriers, which are not confined, flows toward the opposite electrode. Thus, when the active layer including the nano grains is repeatedly laminated, the carriers that are not confined in the first nanophase active layer can be confined in the next nanophase active layer, resulting in improvement in the performance of the cell.

[0064] Moreover, the size and composition of the nano grains of each layer can be changed to emit white light. In addition to monochromatic light, lights with various wavelengths can be simultaneously emitted.

[0065]FIG. 7 is a graph showing the current-voltage characteristic curve obtained by measuring the current-voltage characteristic of a device structure fabricated in a manner that a metal contact is formed on the top and bottom of the sample described in FIG. 6. The curve of FIG. 7 shows negative differential resistance characteristic in the forward bias region. This characteristic means that hole or electron carriers exhibit resonant tunneling phenomenon when the device emits light.

[0066] The peak-to-valley current ratio was 2.1 at the room temperature. The performance of the resonant tunneling light-emitting diode (RTLED) in nanometer size using the GaN nano grains embedded in the amorphous silicon nitride layer (base) 200 can be improved when the highly doped p⁺-silicon substrate 100, optimized GaN nanophase and highly doped n⁻-AlInGaN layer are used.

[0067]FIG. 8 is a schematic cross-sectional view showing the structure of the diode of FIG. 7, and FIG. 9 is a schematic cross-sectional view showing the structure of one of the InGaN/GaN multiple quantum wells (nanophase) 300 of FIG. 8.

[0068] As shown in FIG. 9, the multiple quantum well layers (nanophases) 300 are made in such a manner that an InGaN quantum well 310, a GaN quantum barrier 320, an InGaN 330, a GaN 340, an InGaN 350 and a GaN 360 are sequentially formed.

[0069] The structure of the opto-electronic cell proposed by the present invention can be used in various ways such as resonant tunneling diode, light-emitting diode, light detector and the like by partly changing the type of the substrate and the structure of metal contact. Furthermore, it is possible to fabricate an opto-electronic cell in nanometer size, composed of GaN single grain in nanometer size embedded in the amorphous silicon nitride layer (base) 200. Moreover, an opto-electronic cell that does not require a p-type GaN thin film can be manufactured.

[0070] Preferred embodiments of the present invention will be described hereinafter in order to explain the present invention in more detail. However, the present invention is not limited to the following embodiments, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

[0071] [Embodiment 1]

[0072] The p-type silicon substrate 100 was thermally nitrided using ammonia for 1 to 5 minutes at 900 to 1050° C. in a CVD apparatus, to form the thin amorphous silicon nitride layer 210 thereon, and then GaN nano grains (not shown) were grown on the thin amorphous silicon nitride layer for a predetermined period of time at various temperatures. The amorphous silicon nitride cover layer 220 having the thickness of approximately 20 nm was grown on the amorphous silicon nitride layer and the GaN nano grains using a CVD system. The size and density of crystal grains in nanometer size were controlled by changing growth parameters such as quantity of gallium source (1 to 1000 micromole/min), growth time (1 to 300 sec), growth temperature (500 to 1050° C.) and the like. The size of the nano grain can be changed from several to hundreds nanometers.

[0073] [Embodiment 2]

[0074] The p-type silicon substrate 100 was nitrided using ammonia for 1 to 5 minutes at 900 to 1050° C. in a CVD apparatus, to form the thin amorphous silicon nitride layer 210 thereon, and then AlInGaN nano grains were grown on the thin amorphous silicon nitride layer for a predetermined period of time at various temperatures. The size and density of the AlInGaN nano grains were controlled by changing growth parameters such as quantities of gallium and aluminum sources (1 to 100 micromole/min), growth time (1 to 300 sec), quantity of indium source (1 to 500 micromole/min), growth temperature (500 to 800° C.) and the like. The flow rate of ammonia was 9100 standard cubic centimeter/min (sccm) when the AlInGaN nano grains was grown. The amorphous silicon nitride cover layer 220 having a thickness of about 20 nm was grown on the amorphous silicon nitride layer and the nitride nano grains using a CVD system.

[0075] [Embodiment 3]

[0076] The p-type silicon substrate 100 was nitrided using ammonia for 5 minutes at 900° C. in a CVD apparatus, to form the thin amorphous silicon nitride layer 210 thereon, and then GaN nano grains (not shown) were grown thereon for one minute at the same temperature. Then, the growth temperature is reduced to 700 to 800° C. and quantities of gallium and indium sources and ammonia gas were adjusted to grow InGaN nano grains on the GaN nano grains for a predetermined period of time. The amorphous silicon nitride cover layer 220 having a thickness of about 20 nm was grown on the amorphous silicon nitride layer 210 and the InGaN nanophase using a CVD system.

[0077] [Embodiment 4]

[0078] The p-type silicon substrate 100 was nitrided using ammonia for 5 minutes at 900° C. in a CVD apparatus to form the thin amorphous silicon nitride layer 210, and then GaN nano grains (not shown) were grown on the thin amorphous silicon nitride layer 210 for one minute at the same temperature. Then, the growth temperature is lowered to 700 to 800° C., and three to ten pairs of AlInGaN/AlInGaN multiple quantum well layers 300 were grown on the formed GaN nano grains. The amorphous silicon nitride cover layer 220 having a thickness of about 20 nm was grown on the amorphous silicon nitride layer and the multiple quantum wells using a CVD system.

[0079] [Embodiment 5]

[0080] Metal contact layers 400 and 410 having various structures are respectively formed on the top and bottom of each of the samples in various structures grown in the embodiment 4 using nickel, gold, titanium, aluminum, platinum, ruthenium or transparent metal oxide, for example, nickel oxide. As a result of measurement of the current-voltage characteristic, the characteristics of light-emitting diode, resonant tunneling diode and resonant tunneling light-emitting diode can be obtained at constant temperature according to the structure of the metal contact.

[0081] [Embodiment 6]

[0082] N-type GaN or n-type AlInGaN was grown on the top of each of the samples having various structures, grown in the embodiment 4, and then the metal contact layers 400 and 410 of various structures were respectively formed on the top and bottom of the sample using titanium (Ti), aluminum (Al), gold (Au) or transparent metal oxides. As a measurement result of the current-voltage characteristic, the light-emitting diode characteristic can be obtained at constant temperature.

[0083] The III-nitride compound semiconductor nanophase opto-electronic cell and the fabrication method thereof according to the present invention are free from the problems of the conventional III-nitride compound semiconductor thin film growth on silicon substrates. Accordingly, a high-quality nitride semiconductor nanophase opto-electronic cell having no crystalline defect can be provided. Furthermore, the opto-electronic cell according to the present invention does not require a p-type GaN thin film so that there is no possibility of causing crack that is a problem in the conventional method of fabricating a III-nitride compound semiconductor opto-electronic cell using III-nitride thin films grown on silicon substrates. In addition, the number of processes of fabricating the cell is remarkably reduced to result in an economical and productive opto-electronic cell fabrication process. Moreover, the opto-electronic cell is fabricated using new high-quality GaN-based nanostructures having no crystalline defect to enable the development of a new functional opto-electronic cell in nanometer size. This remarkably enlarges the applicable range of III-nitride compound semiconductor device.

[0084] The forgoing embodiments are merely exemplary and are not to be construed as limiting the present invention. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. 

1. A III-nitride compound semiconductor nanophase opto-electronic cell, comprising: a silicon substrate; and an amorphous silicon nitride layer (base) formed on the substrate and including III-nitride compound semiconductor nano grains spontaneously formed therein.
 2. The III-nitride compound semiconductor nanophase opto-electronic cell as claimed in claim 1, further comprising an electron injection layer formed on the amorphous silicon nitride layer (base).
 3. The III-nitride compound semiconductor nanophase opto-electronic cell as claimed in claim 1 or 2, wherein the III-nitride compound semiconductor nano grains 230 are nano grains of Al_(x)In_(y)Ga_(1-x-y)N (0≦x, y≦1), nano grains of Al_(x)In_(y)Ga_(1-x-y)N/Al_(i)In_(j)Ga_(1-i-j)N (0≦x, y, i, j≦1) forming multiple quantum well structrues, or nano grains of Al_(x)In_(y)Ga_(1-x-y)N/Al_(i)In_(j)Ga_(1-i-j)N (0≦x, y, i, j≦1) forming multiple quantum well structures formed on the nano grains of Al_(x)In_(y)Ga_(1-x-y)N (0≦x, y≦1).
 4. The nitride semiconductor nanophase opto-electronic cell as claimed in claim 3, wherein the nano grain of Al_(x)In_(y)Ga_(1-x-y)N/Al_(i)In_(j)Ga_(1-i-j)N (0≦x, y, i, j≦1) is 3 to 500 nm in diameter.
 5. The nitride semiconductor nanophase opto-electronic cell as claimed in claim 3, wherein the multiple quantum well structures are formed in such a manner that one to twenty pairs of nano grain layers of Al_(x)In_(y)Ga_(1-x-y)N/Al_(i)In_(j)Ga_(1-i-j)N (0≦x, y, i, j≦1) are repeatedly laminated, and each of the nano grain layer is 1 to 20 nm in thickness.
 6. The nitride semiconductor nanophase opto-electronic cell as claimed in claim 3, wherein the nano grain of Al_(x)In_(y)Ga_(1-x-y)N (0≦x, y≦1) has a diameter of 1 to 500 nm.
 7. The nitride semiconductor nanophase opto-electronic cell as claimed in claim 2 or one of claims 4 to 6, wherein the electron injection layer is an n-type Al_(x)In_(y)Ga_(1-x-y)N (0≦x, y≦1) layer.
 8. The nitride semiconductor nanophase opto-electronic cell as claimed in claim 7, wherein the n-type Al_(x)In_(y)Ga_(1-x-y)N (0≦x, y≦1) layer is 1 to 500 nm in thickness.
 9. The nitride semiconductor nanophase opto-electronic cell as claimed in claim 1, wherein the silicon substrate is a p-type silicon substrate.
 10. A method of fabricating an opto-electronic cell using III-nitride compound semiconductor nano grains, comprising the steps of: (a) growing an amorphous silicon nitride layer on a silicon substrate; (b) growing III-nitride compound semiconductor nano grains on the amorphous silicon nitride layer; and (c) growing an amorphous silicon nitride cover layer on the amorphous silicon nitride layer and the III-nitride compound semiconductor nano grains grown on the amorphous silicon nitride layer.
 11. The method as claimed in claim 10, wherein in the step (a), the amorphous silicon nitride layer has a thickness of 1 to 50 nm at 25 to 1100° C.
 12. The method as claimed in claim 10, wherein in the step (c), the amorphous silicon nitride cover layer has a thickness of 1 to 50 nm.
 13. The method as claimed in one of claims 10 to 12, wherein the step (b) further comprises: (d) growing nano grains of Al_(x)In_(y)Ga_(1-x-y)N (0≦x, y≦1) on the amorphous silicon nitride layer; or (e) growing multiple quantum well layers of Al_(x)In_(y)Ga_(1-x-y)N/Al_(x)In_(j)Ga_(1-i-j)N (0≦x, y, i, j≦1) on the amorphous silicon nitride layer; or (f) growing nano grains of Al_(x)In_(y)Ga_(1-x-y)N (0≦x, y≦1) on the amorphous silicon nitride layer, and then growing multiple quantum well layers of Al_(x)In_(y)Ga_(1-x-y)N/Al_(i)In_(j)Ga_(1-i-j)N (0≦x, y, i, j≦1) on the grown nano grains of Al_(x)In_(y)Ga_(1-x-y)N (0≦x, y≦1).
 14. The method as claimed in claim 13, wherein the nano grains of Al_(x)In_(y)Ga_(1-x-y)N (0≦x, y≦1) have a diameter of 1 to 500 nm at 25 to 1100° C. in the steps (d) and (f).
 15. The method as claimed in claim 13, wherein the multiple quantum well layers of Al_(x)In_(y)Ga_(1-x-y)N/Al_(i)In_(j)Ga_(1-i-j)N (0≦x, y, i, j≦1) are grown at 500 to 1100° C. in the steps (e) and (f).
 16. The method as claimed in claim 13, wherein the multiple quantum well layers of Al_(x)In_(y)Ga_(1-x-y)N/Al_(i)In_(j)Ga_(1-i-j)N (0≦x, y, i, j≦1) include one to twenty pairs of the multiple quantum well layers.
 17. The method as claimed in claim 13, wherein the nano grain of Al_(x)In_(y)Ga_(1-x-y)N (0≦x, y≦1) grown in the step (d) is 1 to 20 nm in diameter, and the amorphous silicon nitride cover layer formed in the step (c) is 1 to 20 nm in thickness.
 18. The method as claimed in claim 17, further comprising a step of repeatedly performing, once to twenty times, a process of growing nano grains of Al_(x)In_(y)Ga_(1-x-y)N (0≦x, y≦1), nano grains of Al_(x)In_(y)Ga_(1-x-y)N/Al_(i)In_(j)Ga_(1-i-j)N (0≦x, y, i, j≦1) forming multiple quantum well structures, or nano grains of Al_(x)In_(y)Ga_(1-x-y)N/Al_(i)In_(j)Ga_(1-i-j)N (0≦x, y, i, j≦1) forming multiple quantum well structures formed on the nano grains of Al_(x)In_(y)Ga_(1-x-y)N (0≦x, y≦1) on the amorphous silicon nitride cover layer, and then growing the amorphous silicon nitride cover layer on any one of the three nano grains. 